Bedingungen für die Teilnahme (technische und berufliche Fähigkeiten)
with the following minimum requirements for the references.
The references must not be older than 5 years and must be described in detail as to prove the following experiences:
- Experience in design, layout and test of tailored custom solutions with long-term accelerator operation in mind.
- Practical project experience with the design and implementation of customer-specific solutions in the field of large-scale research facilities and ideally already experience in the setup and operation of overall systems at accelerator facilities.
- Solutions, realized on modular concepts in close collaboration with the customer in order to incorporate the specific hardware and software interfaces of the accelerator complex.
- Experience in design, development and characterization of low-noise analogue electronics
- Experience in design, development, programming and debugging of state-of-the-art high-performance digital acquisition electronics with online digital signal processing in FPGAs.
- Experience in selection of radiation tolerant electronic components for front-end electronics, here the BPM pre-amplifiers, installed in the accelerator tunnels or niches.
- Experience with automation and data acquisition at accelerator facilities.
- Experience in the manufacture of UHV-capable drives, the execution of vacuum acceptance procedures and with the creation of the necessary software.
- Experience with the procurement, installation (commissioning), programming and maintenance of PLC-based controls and associated electronic components.
- Experience with the development and construction of state-of-the-art electronics, especially in the MüTCA standard.
- Experience with the integration of external electronics via standardized interfaces, especially knowledge of the White Rabbit Timing System and its special timing receiver nodes.
- Experience with Intel/Altera Quartus Design Suite programming, with VHDL, with Intel/Altera Arria10 FPGA family, with Intel/Altera MAX10 FPGA family and with Arria10 FPGA power sequencing.
- Experience with the development and adaptation of special software for accelerator systems and with the corresponding integration into such systems (with Linux operating system).
- Experience with the development and maintenance of FESA classes and the necessary interfaces with connection to other important con-trol system components (LSA, timing system, etc.).
- Extensive project experience in the development of control system software and the corresponding development languages (listing required).
- Many years of experience in programming in the languages C++ and Java/JavaFX, profound knowledge of the software framework FESA (Front-End Software Architecture), in the creation of FESA applica-tions, in the familiarization with complex software frameworks (e.g. specific control system infrastructure of an accelerator), knowledge of standardized tools for the management of software projects (GIT, Subversion SVN, or similar), with SILECS Framework and with UNICOS Industrial Controls Framework.
- Experience with macro development for Rackplan, the Machinery Directive DIN EN 13849-1 and DIN EN 60204-1 and with WinCC-OA, S7 PLC, TIA Portal, S7 safety programming.